The interest in high performance three-dimensional (3D) imaging has grown in recent years due to immense demand in engineering, science, medicine and entertainment domains. The driving goals of state-of-the-art 3D imagers are high sensitivity to light and fine depth resolution at long range. Furthermore, high level of integration is desirable to achieve low system cost. To meet these demands, the industry has started to transition from traditional analog techniques to standard CMOS based solutions. A key component of a 3D imager is a time-to-digital converter (TDC).
Known TDC schemes, especially those used for Time to Distance conversions, comprise a Coarse-Fine architecture where the most power consuming part, the coarse interpolator, is active throughout to count the clock cycles. It has been found that these known schemes have high power consumption when used in imager applications.